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ARD2
1.00 for Rev B. Hardware
Airbag Reference Demonstrator using MPC5604P
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Upper layer of scheduler in charge of scheduling deliveries. More...
#include "derivative.h"#include "PIT.h"#include "eDMA.h"#include "MailDelivery.h"#include "MailScheduler.h"#include "Compile_options.h"Functions | |
| uint8_t | u8fnSchedConfig (uint32_t u32PITCnt, uint8_t u8PITCh, uint32_t u32ReSchCnt, uint8_t u8ReSchPITCh) |
| Configures PIT channel u8PITCh as timer for the scheduler. It also configures a secondary channel for re-scheduling events. | |
| uint8_t | u8fnSchedEnable (uint8_t u8Enable) |
| Enables or disables the message scheduler. | |
| uint8_t | u8fnSchedDSPIMailTransfer (uint8_t u8DSPIInstance, uint8_t u8CS, uint8_t u8ContCS, uint8_t u8EndOfQueueFlag, uint16_t *pu16MsgSrc, uint16_t *pu16MsgResponse, uint16_t u16Size) |
| Schedules an SPI transfer for the next tick. This routine should not be interrupted by Isrs. | |
| uint8_t | u8fnSchedCompositeDSPIMailTransfer (const uint8_t u8DSPIInstance1, const uint8_t u8DSPIInstance2, const uint8_t u8CS, uint16_t *pu16MsgSrc1, uint16_t *pu16MsgSrc2, const uint16_t *pu16MsgResponse, uint16_t u16SizeAtOrigin) |
| Schedules an SPI transfer for the next tick. It combines two CTAR locations to perform transfers that are either longer than 16-bits or have an unusual number of bits. | |
| uint32_t | u32fnSchedHasTimeElapsed (uint32_t u32MyTickCount) |
| Returns the number of ticks since u32MyTickCount. | |
| uint32_t | u32fnSchedIsTxDone (uint32_t u32MyTxTime) |
| Returns u32MyCount - the last value set by TxDone Isr. | |
| void | vfnSchedIsr (void) |
| Isr to be called every time PIT expires (every time a tick occurs) | |
| void | vfnSchedInboxDoneIsr (void) |
| Isr to be called when the inbox has been filled . It sorts DMA channels out. | |
| void | vfnReschedulerIsr (void) |
| This routine will be invoked when the Rescheduling PIT value expires. Drivers can build on it to reschedule their message if necessary. | |
Variables | |
| vuint32_t | gu32SchedTickCount |
| vuint32_t | gu32SchedTxDoneCount |
| vuint8_t | gu8RescheduleSource |
| uint8_t | gu8ReSchPITCh |
Upper layer of scheduler in charge of scheduling deliveries.
Copyright (c) 2011 Freescale Semiconductor Freescale Confidential Proprietary
History:
| uint32_t u32fnSchedHasTimeElapsed | ( | uint32_t | u32MyTickCount | ) |
Returns the number of ticks since u32MyTickCount.
| u32MyTickCount,: | A particular moment in time |
| uint32_t u32fnSchedIsTxDone | ( | uint32_t | u32MyTickCount | ) |
Returns u32MyCount - the last value set by TxDone Isr.
| u32MyTickCount,: | A particular moment in time |
| uint8_t u8fnSchedCompositeDSPIMailTransfer | ( | const uint8_t | u8DSPIInstance1, |
| const uint8_t | u8DSPIInstance2, | ||
| const uint8_t | u8CS, | ||
| uint16_t * | pu16MsgSrc1, | ||
| uint16_t * | pu16MsgSrc2, | ||
| const uint16_t * | pu16MsgResponse, | ||
| uint16_t | u16SizeAtOrigin | ||
| ) |
Schedules an SPI transfer for the next tick. It combines two CTAR locations to perform transfers that are either longer than 16-bits or have an unusual number of bits.
| u8DSPIInstance1,: | SPI instance and memory to be used for the first word. |
| u8DSPIInstance2,: | SPI instance and memory to be used for the second word. |
| u8CS,: | Chip select to be used. |
| pu16MsgSrc1,: | pointer to the message source for the first word |
| pu16MsgSrc2,: | pointer to the message source for the second word |
| pu16MsgResponse,: | pointer to the location where the response should be stored. Note that the number of words stored is that of u16SizeOfOrigin * 2 |
| u16Size,: | Size of composite transfers. |
| uint8_t u8fnSchedConfig | ( | uint32_t | u32PITCnt, |
| uint8_t | u8PITCh, | ||
| uint32_t | u32ReSchCnt, | ||
| uint8_t | u8ReSchPITCh | ||
| ) |
Configures PIT channel u8PITCh as timer for the scheduler. It also configures a secondary channel for re-scheduling events.
| u32PITCnt,: | Number of counts that must expire before creating a scheduler interrupt. Counts are at bus frequency. |
| u8PITCh,: | Active PIT channel for scheduler. It will be stored for future use. |
| u32ReSchCnt,: | Number of counts that must expire before creating a re-schedule interrupt. |
| u8ReSchPITCh,: | Active PIT channel for re-scheduler. |
| uint8_t u8fnSchedDSPIMailTransfer | ( | uint8_t | u8DSPIInstance, |
| uint8_t | u8CS, | ||
| uint8_t | u8ContCS, | ||
| uint8_t | u8EndOfQueueFlag, | ||
| uint16_t * | pu16MsgSrc, | ||
| uint16_t * | pu16MsgResponse, | ||
| uint16_t | u16Size | ||
| ) |
Schedules an SPI transfer for the next tick. This routine should not be interrupted by Isrs.
| u8DSPIInstance,: | SPI instance and memory to be used. |
| u8CS,: | Chip select to be used. |
| u8EndofQueueFlag,: | Enable or disable EndOfQueue flag (and ISR). |
| pu16MsgSrc,: | pointer to the message source |
| pu16MsgResponse,: | pointer to the location where the response should be stored. |
| u16Size,: | Size of transfer in number of words. |
| uint8_t u8fnSchedEnable | ( | uint8_t | u8Enable | ) |
Enables or disables the message scheduler.
| u8Enable,: | If non-zero, enables, otherwise disables. |
| void vfnReschedulerIsr | ( | void | ) |
This routine will be invoked when the Rescheduling PIT value expires. Drivers can build on it to reschedule their message if necessary.
| None |
| void vfnSchedInboxDoneIsr | ( | void | ) |
Isr to be called when the inbox has been filled . It sorts DMA channels out.
| None |
| void vfnSchedIsr | ( | void | ) |
Isr to be called every time PIT expires (every time a tick occurs)
| None |